High performance microelectronic or semiconductor devices often use solder bumps ("bumps") for electrical and mechanical connection to other microelectronic devices or substrates. This connection technology is commonly referred to as "flip-chip" technology.
In the flip-chip technology, a plurality of bumps formed of low melting point metal is provided in a predetermined position ("bump pattern") on the surface of a semiconductor substrate on which active elements are formed. The semiconductor substrate is then connected to a circuit board or another substrate, such as a flip-chip package. The package includes pads that are the mirror image of the bump pattern on the semiconductor substrate. The semiconductor substrate is connected to the flip-chip package at one time by reflow melting of the bumps.
One of the drawbacks of the conventional flip-chip technology is that for each semiconductor device, a custom bump pattern is provided on the associated semiconductor substrate, which in turn requires a custom package with a custom pad pattern that mirrors the bump pattern on the semiconductor substrate. The requirements for custom packages adversely increase the design cycle time and the cost of using the flip-chip technology.
Attempts have been made in the art to provide generic bump patterns for a semiconductor substrate. However, those attempts have not been very successful as they typically fail to achieve an optimized electrical performance (i.e., higher speed and lower noise) for a large variety of semiconductor devices. A solution which would provide a generic bump patterns on semiconductor substrates while optimizing the electrical performance of the associated semiconductor devices has been long sought but has eluded those skilled in the art. As the semiconductor industry is moving at an increasing pace to higher performance semiconductor devices, it is becoming more pressing that a solution be found.